HyperLynx® Product Family
What’s New in HyperLynx -VX.2.6
The latest releases of HyperLynx address the increasing complexity of today’s advanced system designs through an emphasis on both ease-of-use and team productivity.
New Electrical Design Rule Checks
New electrical design rule checks include analog rules, power integrity rules such as PDN isolation and grounding layer, and creepage rules for ensuring compliance with safety standards. IEC international standards and charts are available with the tool, eliminating the need to reference these documents externally.
Power-Aware PDN Analysis
Power-Aware simulation assesses the effects of non-ideal PDN behavior on signal quality. The effects of Simultaneous Switching Noise (SSN) at the driver and via-to-via coupling through the power planes can be included in signal integrity simulations to determine how they affect system design margin. Use the DDRx wizard to accurately simulate signal/PDN interactions and to simplify the simulation process.
DC Drop for Rigid-Flex & Multi-board
The VX.2.4 release brings additional support for rigid-flex and multi-board analysis. Power integrity enhancements include seamless DC drop simulation and analysis for rigid-flex designs.
SERDES Protocol Compliance
Verify SerDes channel compliance with 34 built-in protocols. The VX.2.4 release adds support for PCIe Gen 1, Gen 2, and Gen 5, 50GBASE-CR, and JESD204C-JCOM. Usability improvements include the addition of FastEye capabilities (without the need for IC models), to the SerDes batch wizard.
Effective Return Loss (ERL)
Effective Return Loss is a new way of assessing return loss in high-speed serial channels. Although multiple steps are required to compute ERL, HyperLynx automates the process to provide a more-efficient way of tracking COM. HyperLynx is the only tool capable of measuring ERL for 50GBASE-KR and 50GBASE-CR SerDes channels.
Net Coupling Using Electrical dB Thresholds
Determine the coupling potential of nets at different dB. HyperLynx takes package coupling, connector coupling, and 3D-area and power-aware SI model coupling into account. Simplify your design calculations by using the same threshold for all nets or add separate values for more accurate simulation.
New to HyperLynx BoardSim is constraint integration, enabling you to create a wide range of signal integrity constraints and net class assignments. For comprehensive batch SI analysis, you can also import constraints directly from Xpedition schematic or layout.
Multi-layer safety clearance and creepage rules
Automated high-voltage creepage checks eliminate the tedious work associated with PCB validation and make it easy to find design errors.
Improve work output
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