Design Creation

Whether designing an FPGA or ASIC, the devices have advanced capabilities and complex features that, when put under tight development cycles, burden the design teams to produce efficient and robust chips. Hence, the design teams have placed more demands on HDL processes, automation, and style guidelines for developing quality design results.

Standard languages (such as VHDL, Verilog, SystemVerilog) and IP formats, along with common industry version management systems aid in producing repeatable and dependable design processes, but the tools that utilize these standards need to do much more than edit text files. Mentor Graphics delivers a complete design solution for FPGA and ASIC HDL development beginning with comprehensive design creation addressing new code creation, formal and informal design reuse, and any combination in between. These HDL design capabilities greatly assist engineers, individuals and teams, in creating, analyzing, and managing their complex designs, improving their productivity and accelerating design creation.

Features and Benefits

Key Benefits

  • Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog
  • Accelerates RTL Reuse
  • Extensive design checking rules and rulesets
  • Interactive HDL visualization and creation tools
  • Automatic documentation features and reporting
  • Intelligent debug and analysis
  • Concurrent design entry and checking

SystemVerilog

  • Manage and understand code relationships
  • Accelerate language proficiency and results
  • Summarize and quantify code characteristics
  • Automate and simplify data management
  • Design, measure and document for practical code reuse

Design and Reuse

  • Quickly assess reused code quality and increase design understanding
  • Efficiently create RTL designs using text, tables, and graphics
  • Interactively manage design flow and all project data
  • Rapidly produce documentation
  • Accelerate IP repository population

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