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HyperLynx Full-Wave Solver

HyperLynx® Full-Wave Solver delivers unprecedented speed and capacity, through accelerated boundary element technology, while preserving gold-standard Maxwell accuracy. Achieve greater accuracy and fewer re-spins, even on the most complex structures.

Designers can take advantage of high speed, accuracy and capacity for signal integrity, power integrity and EMI concerns – all from within a common interface. The Full-Wave Solver is built from the ground up to exploit multi-core and hybrid architectures, and to utilize the best of fast solver technology to enable fast simulation on a single core or multiple cores.

Power-aware SI trace model extraction can be performed, as well as DC and AC power integrity analysis at the system (package/PCB) level. Designers can benefit from a power delivery network impedance profile, capacitor loop inductance, and combined signal and power broadband S-parameter extraction for use in time-domain simulation – all within a common, easy-to-use interface.

Full-wave electromagnetic solver

High-capacity, scalable EM solver addresses broadband 3D modeling needs.

Powerful EMI features

Using on-chip noise sources, users can observe near-field and far-field EMI/EMC performance.

Accelerate power-aware SI model extraction

Leverage the same easy-to-use user interface to add system-level hybrid interconnect modeling technology.

Specialized 3D solver optimized for power integrity

Obtain and view S, Y, and Z matrices and loop inductance, visualize induced and return currents, and observe strong coupling paths of your package PCB system.

Powerful DC analysis features

Perform static IR drop analysis to view current flow, voltage gradients, and current density plots.

Technical Specifications
  • Directly imports chip, package, and board geometry in widely used CAD formats and produces output models that are compatible with standard circuit simulation engines
  • Merge utilities within an integrated workspace
  • Seamless silicon-package-board co-analysis
  • Integrated, specialized 3D PI and hybrid power-aware SI model solver technologies
  • High speed and scalability enables designers to perform signoff post-layout verification
  • Broadband formulation enables generation of DC to high-frequency S-parameters from a single tool
  • Obtain S, Y and Z matrices, visualize induced and return currents, improve designs by observing strong coupling paths, create merged chip-package-board 3D models and observe electrical behavior through the integrated system
  • Integrates tightly with existing design flows via powerful Python scripting interface
  • Utilizes accelerated boundary element technology that enables unprecedented speed and capacity, while preserving gold-standard Maxwell accuracy
Parallelization Methodology

This paper discusses the parallelization strategy.

Built upon a two-layer foundation, the strategy includes: (a) fine-grained, multi-threaded solver architectures for the multicore environment (b) coarse-grained, distributed architectures for multiple processors connected by high-speed buses is summarized. This parallelization methodology is tuned to simultaneously exploit the proprietary fast solver technology and to take advantage of emerging multicore and many-core processors.

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